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 PIPELINE BURST CACHE Definition
We define PIPELINE BURST CACHE |
PIPELINE BURST CACHE - A form of L2 cache that uses pipelining to speed data access by being able to feed data to the CPU at the same time as it pulls data from memory. The burst mode also allows the cache to fetch additional data from main memory before the CPU requests it. This type of cache was used back in the Pentium days when L2 cache was separate from the processor. |
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